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PD - 95381
Logic-Level Gate Drive Advanced Process Technology l Surface Mount (IRL3705NS) l Low-profile through-hole (IRL3705NL) l 175C Operating Temperature l Fast Switching l Fully Avalanche Rated l Lead-Free Description
l l
IRL3705NSPbF IRL3705NLPBF
D
HEXFET(R) Power MOSFET VDSS = 55V
G S
RDS(on) = 0.01 ID = 89A
Absolute Maximum Ratings
ID @ TC = 25C ID @ TC = 100C IDM PD @TA = 25C PD @TC = 25C V GS EAS IAR EAR dv/dt TJ TSTG
Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. The D2Pak is a surface mount power package capable of accommodating die sizes up to HEX-4. It provides the highest power capability and the lowest possible onresistance in any existing surface mount package. The D2Pak is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0W in a typical surface mount application. The through-hole version (IRL3705NL) is available for lowprofile applications.
D 2 Pak
TO-262
Parameter
Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Power Dissipation Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds
Max.
89 63 310 3.8 170 1.1 16 340 46 1.7 5.0 -55 to + 175 300 (1.6mm from case )
Units
A W W W/C V mJ A mJ V/ns C
Thermal Resistance
Parameter
RJC RJA Junction-to-Case Junction-to-Ambient ( PCB Mounted,steady-state)**
Typ.

Max.
0.90 40
Units
C/W 06/08/04
IRL3705NS/LPbF
Electrical Characteristics @ TJ = 25C (unless otherwise specified)
Parameter Drain-to-Source Breakdown Voltage V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient V(BR)DSS RDS(on) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf LS Ciss Coss Crss Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Source Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Min. 55 1.0 50 Typ. 0.056 12 140 37 78 Max. Units Conditions V VGS = 0V, ID = 250A V/C Reference to 25C, ID = 1mA 0.010 VGS = 10V, ID = 46A 0.012 VGS = 5.0V, ID = 46A 0.018 VGS = 4.0V, ID = 39A 2.0 V VDS = VGS , ID = 250A S VDS = 25V, ID = 46A 25 VDS = 55V, VGS = 0V A 250 VDS = 44V, V GS = 0V, TJ = 150C 100 VGS = 16V nA -100 VGS = -16V 98 ID = 46A 19 nC VDS = 44V 49 VGS = 5.0V, See Fig. 6 and 13 VDD = 28V ID = 46A ns RG = 1.8, VGS = 5.0V RD = 0.59, See Fig. 10 Between lead, 7.5 nH and center of die contact 3600 VGS = 0V 870 pF VDS = 25V 320 = 1.0MHz, See Fig. 5
Source-Drain Ratings and Characteristics
IS
I SM
V SD t rr Q rr ton Notes:
Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Forward Turn-On Time
Min. Typ. Max. Units
Conditions D MOSFET symbol 89 showing the A G integral reverse 310 S p-n junction diode. 1.3 V TJ = 25C, IS = 46A, VGS = 0V 94 140 ns TJ = 25C, IF = 46A 290 440 nC di/dt = 100A/s Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Repetitive rating; pulse width limited by
RG = 25, IAS = 46A. (See Figure 12)
Pulse width 300s; duty cycle 2%. Uses IRL3705N data and test conditions Calculated continuous current based on maximum allowable
max. junction temperature. ( See fig. 11 )
VDD = 25V, starting TJ = 25C, L = 320H ISD 46A, di/dt 250A/s, VDD V(BR)DSS,
TJ 175C
junction temperature; for recommended current-handling of the package refer to Design Tip # 93-4 ** When mounted on 1" square PCB ( FR-4 or G-10 Material ). For recommended footprint and soldering techniques refer to application note #AN-994.
IRL3705NS/LPbF
1000
VGS 15V 12V 10V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V TOP
1000
ID , Drain-to-Source Current (A)
ID , Drain-to-Source Current (A)
VGS 15V 12V 10V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V TOP
100
100
10
10
2.5V
2.5V 20s PULSE WIDTH T J = 25C
1 10
1 0.1
A
100
1 0.1
20s PULSE WIDTH T J = 175C
1 10
A
100
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
3.0
R DS(on) , Drain-to-Source On Resistance (Normalized)
I D = 77A
I D , Drain-to-Source Current (A)
2.5
TJ = 25C
100
TJ = 175C
2.0
1.5
10
1.0
0.5
1 2.0 3.0 4.0 5.0
V DS= 25V 20s PULSE WIDTH
6.0 7.0 8.0
A
0.0 -60 -40 -20 0 20 40 60
VGS = 10V
80 100 120 140 160 180
A
VGS , Gate-to-Source Voltage (V)
TJ , Junction Temperature (C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance Vs. Temperature
IRL3705NS/LPbF
6000
5000
4000
V GS , Gate-to-Source Voltage (V)
V GS = 0V, f = 1MHz C iss = Cgs + C gd , Cds SHORTED C rss = C gd Ciss C oss = C ds + C gd
15
I D = 46A V DS = 44V V DS = 28V
12
C, Capacitance (pF)
9
3000
Coss
6
2000
Crss
1000
3
0 1 10 100
A
0 0 20 40 60
FOR TEST CIRCUIT SEE FIGURE 13
80 100 120 140
A
VDS , Drain-to-Source Voltage (V)
Q G , Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage
1000
1000
ISD , Reverse Drain Current (A)
OPERATION IN THIS AREA LIMITED BY R DS(on)
10s 100 100s
100
TJ = 175C TJ = 25C
I D , Drain Current (A)
1ms 10 10ms
10 0.4 0.8 1.2 1.6 2.0
VGS = 0V
2.4
A
1 1
TC = 25C TJ = 175C Single Pulse
10
A
100
2.8
VSD , Source-to-Drain Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
IRL3705NS/LPbF
100
LIMITED BY PACKAGE
80
V DS V GS RG
RD
D.U.T. V DD +
I D , Drain Current (A)
60
5.0V
Pulse Width 1 s Duty Factor 0.1 %
40
Fig 10a. Switching Time Test Circuit
20
VDS 90%
0 25 50 75 100 125 150 175
TC , Case Temperature ( C)
Fig 9. Maximum Drain Current Vs. Case Temperature
10% VGS
td(on) tr t d(off) tf
Fig 10b. Switching Time Waveforms
1
Thermal Response (Z thJC )
D = 0.50
0.20 0.10 0.05 0.02 0.01 SINGLE PULSE (THERMAL RESPONSE) PDM t1 t2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thJC + TC 0.0001 0.001 0.01 0.1 1
0.1
0.01 0.00001
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
IRL3705NS/LPbF
E AS , Single Pulse Avalanche Energy (mJ)
800
TOP BOTTOM
600
15V
ID 19A 33A 46A
VDS
L
DRIVER
400
RG
10V
D.U.T
IAS tp
+ V - DD
A
0.01
200
Fig 12a. Unclamped Inductive Test Circuit
0
VDD = 25V
25 50 75 100 125 150
A
175
V(BR)DSS tp
Starting TJ , Junction Temperature (C)
Fig 12c. Maximum Avalanche Energy Vs. Drain Current
I AS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator Same Type as D.U.T.
50K
QG
12V
.2F .3F
5.0 V
QGS VG QGD
VGS
3mA
D.U.T.
+ V - DS
Charge
IG
ID
Current Sampling Resistors
Fig 13a. Basic Gate Charge Waveform
Fig 13b. Gate Charge Test Circuit
IRL3705NS/LPbF
Peak Diode Recovery dv/dt Test Circuit
D.U.T
+
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
-
+
RG * * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
+ V DD
Driver Gate Drive P.W. Period D=
P.W. Period VGS=10V
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
VDD
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple 5%
ISD
* VGS
= 5V for Logic Level Devices
Fig 14. For N-Channel HEXFETS
IRL3705NS/LPbF
D2Pak Package Outline
Dimensions are shown in millimeters (inches)
D2Pak Part Marking Information
T HIS IS AN IRF 530S WIT H LOT CODE 8024 ASS E MBL ED ON WW 02, 2000 IN T HE AS S E MBLY L INE "L" Note: "P" in as s embly line pos ition indicates "Lead-F ree" INT E RNAT IONAL RECT IF IE R LOGO AS S EMB LY LOT CODE PART NUMBE R F 530S DAT E CODE YEAR 0 = 2000 WE EK 02 LINE L
OR
INT ERNAT IONAL RE CT IF IER LOGO AS S E MBLY LOT CODE PAR T NUMBER F530S DAT E CODE P = DE S IGNAT ES LEAD-F REE PRODU CT (OPT IONAL) YEAR 0 = 2000 WEEK 02 A = AS S EMBLY S ITE CODE
IRL3705NS/LPbF
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
E XAMPL E: T HIS IS AN IRL 3103L LOT CODE 1789 AS S E MB L ED ON WW 19, 1997 IN T HE AS S E MBL Y LINE "C" Note: "P" in ass embly line pos ition indicates "Lead-F ree" INT E RNAT IONAL RE CT IF IER LOGO AS S EMBL Y L OT CODE PART NUMBE R
DAT E CODE YE AR 7 = 1997 WE EK 19 L INE C
OR
INT ERNAT IONAL RE CT IF IER L OGO AS S E MB LY L OT CODE PART NUMB ER DAT E CODE P = DES IGNAT ES L EAD-FREE PRODUCT (OPT IONAL ) YE AR 7 = 1997 WEE K 19 A = AS S E MB LY S IT E CODE
IRL3705NS/LPbF
D2Pak Tape & Reel Information
Dimensions are shown in millimeters (inches)
TRR
1.60 (.063) 1.50 (.059) 4.10 (.161) 3.90 (.153)
1.60 (.063) 1.50 (.059) 0.368 (.0145) 0.342 (.0135)
FEED DIRECTION 1.85 (.073)
1.65 (.065)
11.60 (.457) 11.40 (.449)
15.42 (.609) 15.22 (.601)
24.30 (.957) 23.90 (.941)
TRL
10.90 (.429) 10.70 (.421) 1.75 (.069) 1.25 (.049) 16.10 (.634) 15.90 (.626) 4.72 (.136) 4.52 (.178)
FEED DIRECTION
13.50 (.532) 12.80 (.504)
27.40 (1.079) 23.90 (.941)
4
330.00 (14.173) MAX.
60.00 (2.362) MIN.
NOTES : 1. COMFORMS TO EIA-418. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION MEASURED @ HUB. 4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
30.40 (1.197) MAX.
26.40 (1.039) 24.40 (.961) 3
4
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 06/04

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